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| Features * 64-megabit (4M x 16) and 32-megabit (2M x 16) Flash Memories * 1.65V - 1.95V Read/Write * High Performance - Random Access Time - 90 ns - Page Mode Read Time - 20 ns - Synchronous Burst Frequency - 54 MHz - Configurable Burst Operation Sector Erase Architecture - Eight 4K Word Sectors with Individual Write Lockout - 32K Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: 32K Word Sectors - 500 ms; 4K Word Sectors - 100 ms 32M, Dual Plane Organization, Permitting Concurrent Read while Program/Erase - Memory Plane A: 25% of Memory Including Eight 4K Word Sectors - Memory Plane B: 75% of Memory Consisting of 32K Word Sectors 64M, Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not Being Programmed/Erased - Memory Plane A: 25% of Memory Including Eight 4K Word Sectors - Memory Plane B: 25% of Memory Consisting of 32K Word Sectors - Memory Plane C: 25% of Memory Consisting of 32K Word Sectors - Memory Plane D: 25% of Memory Consisting of 32K Word Sectors Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 30 mA Active - 10 A Standby Data Polling and Toggle Bit for End of Program Detection VPP Pin for Write Protection and Accelerated Program/Erase Operations RESET Input for Device Initialization CBGA Package Top or Bottom Boot Block Configuration Available 128-bit Protection Register Common Flash Interface (CFI) * * * * * 64-megabit (4M x 16) and 32-megabit (2M x 16) Burst/Page Mode 1.8-volt Flash Memory AT49SN6416 AT49SN6416T AT49SN3208 AT49SN3208T Advance Information * * * * * * * * Description The AT49SN6416(T) and AT49SN3208(T) are 1.8-volt 64-megabit and 32-megabit Flash memories respectively. The memories are divided into multiple sectors and planes for erase operations. The devices can be read or reprogrammed off a single 1.8V power supply, making them ideally suited for in-system programming. The devices can be configured to operate in the asynchronous/page read (default mode) or burst read mode. The burst read mode is used to achieve a faster data rate than is possible in the asynchronous/page read mode. If the AVD and the CLK signals are both tied to GND, the device will behave like a standard asynchronous Flash memory. In the page mode, the AVD signal can be tied to GND or can be pulsed low to latch the page address. In both cases the CLK can be tied to GND. The AT49SN3208(T) is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. The AT49SN6416(T) is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains Rev. 1605C-FLASH-03/02 1 an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in the other memory plane. The end of program or erase is detected by Data Polling or toggle bit. The VPP pin provides data protection and faster programming and erase times. When the VPP input is below 0.8V, the program and erase functions are inhibited. When V PP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 12.0V, the program and erase operations are accelerated. With V PP at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, by taking the RESET pin to GND or by a high-to-low transition on the VPP input. Erase, Erase Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. Pin Configurations Pin Name I/O0 - I/O15 A0 - A21 CE OE WE AVD CLK RESET WP VPP RDY VCCQ Note: Pin Function Data Inputs/Outputs Addresses(1) Chip Enable Output Enable Write Enable Address Latch Enable Clock Reset Write Protect Write Protection and Power Supply for Accelerated Program/Erase Operations Ready Output Power Supply 1. For the AT49SN6416(T), the address bits are A0 - A21, and for the AT49SN3208(T), the address bits are A0 - A20. In the following text, address bits A0 - A21 will be used when referring to both devices. CBGA Top View 1 2 3 4 5 6 7 8 A A11 A8 VSS VCC VPP A18 A6 A4 B A12 A9 A20 CLK RESET A17 A5 A3 C A13 A10 A21* AVD WE A19 A7 A2 D A15 A14 RDY A16 I/O12 WP A1 E VCCQ I/O15 I/O6 I/O4 I/O2 I/O1 CE A0 F VSS I/O14 I/013 I/O11 I/O10 I/O9 I/O0 OE G I/O7 VSSQ I/O5 VCC I/O3 VCCQ I/O8 VSSQ *A21 is a NC for the AT49SN3208(T). 2 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Device Operation COMMAND SEQUENCES: The device powers on in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. After the completion of a program or an erase cycle, the device enters the read mode. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on the AVD signal or the rising edge of the first clock pulse when AVD is low, whichever occurs first. If the AVD is not pulsed low, the address will be latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. BURST CONFIGURATION COMMAND: The Program Burst Configuration Register command is used to program the burst configuration register. The burst configuration register determines several parameters that control the read operation of the device. Bit B15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. Since the page read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to enable the page read feature. Bit B14 determines whether a four word page or an eight word page will be used. The rest of the bits in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock latency versus input clock frequency table is shown on page 15. The "Burst Read Waveform" as shown on page 28 illustrates a clock latency of four; the data is output from the device four clock cycles after the first low-to-high clock edge following the high-to-low AVD edge. The B10 bit of the configuration register determines the polarity of the RDY signal. The B9 bit of the burst configuration register determines the number of clocks that data will be held valid (see Figure 1). The B8 bit of the burst configuration register determines when the RDY signal will be asserted. When synchronous burst reads are enabled, an interleaved or linear burst sequence can be selected by setting bit B7. Table 4 shows the difference between the interleaved and burst sequence. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four- or eight-word length will be used in the fixed-length mode. When a four or eight word burst length is selected, Bit B3 can be used to select whether burst accesses wrap within the burst length boundary or whether they cross word length boundaries to perform linear accesses. Please see Table 4. All other bits in the burst configuration register should be programmed as shown on page 15. The default state (after power-up or reset) of the burst configuration register is also shown on page 15. To read the burst configuration register, the Product ID Entry command is given, followed by a normal read operation from address location 00005H. After reading the burst configuration register, the Product ID Exit command must be given prior to performing any other operation. ASYNCHRONOUS READ: There are two types of asynchronous reads - AVD pulsed and standard asynchronous reads. The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. The data at the address location defined by A0 - A21 and captured by the AVD signal will be read when CE and OE are low. The address location passes into the device when CE and AVD are low; the address is latched on the low-to-high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of the device. The access time is measured from stable address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are shown on page 25. 3 1605C-FLASH-03/02 PAGE READ: The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input is ignored during a page read operation and should be tied to GND. The page size can be four words (default value) or eight words depending on what value bit B14 of the burst configuration register is programmed to. During a page read, the AVD signal can transition low and then transition high, transition low and remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (determined by A21 - A3 for an eight word page and A21 - A2 for a four word page) cannot change during a page read operation. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 90 ns. Once the first word is read, toggling A0 and A1 (four word page mode) or toggling A0, A1, and A2 (eight word page mode) will result in subsequent reads within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to GND, the device will behave like a standard asynchronous Flash memory. The page read diagrams are shown on page 26. SYNCHRONOUS READS: Synchronous reads are used to achieve a faster data rate than is possible in the asynchronous/page read mode. The device can be configured for continuous or fixed-length burst access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs. The initial read location is determined as for the AVD pulsed asynchronous read operation; it can be any memory location in the device. In the burst access, the address is latched on the rising edge of the first clock pulse when AVD is low or the rising edge of the AVD signal, whichever occurs first. The CLK input signal controls the flow of data from the device for a burst operation. After the clock latency cycles, the data at the next burst address location is read for each following clock cycle. CONTINUOUS BURST READ: During a continuous burst read, any number of addresses can be read from the memory. When a page boundary in the memory is transitioned, additional time may be required for the device to continue the burst read. To indicate that it is not ready to continue the burst, the device will drive the RDY pin low (B10 = 0) during the clock cycles in which new data is not being presented. Once the RDY pin is driven high (B10 = 0), the next data will be valid. Starting with address zero, page boundaries occur every 128 words in the memory. During a continuous burst read, the first page boundary transition may occur before 128 words are read, depending on the initial burst address. The RDY signal will be tri-stated when the CE or OE signal is high. In the "Burst Read Waveform" as shown on page 28, data D0 is valid asynchronously from point A, the time when the addresses are latched. D0 is valid within 13.5 ns of the clock edge for the specified clock latency (the waveforms show a clock latency of four). The low-to-high transition of the clock at point C results in D1 being read. The transition of the clock at point D results in a burst read of the last word of the page, D127. The clock transition at point E does not cause new data to appear on the output lines because the RDY signal goes low (B10 and B8 = 0) after the clock transition, which signifies that a page boundary in the memory has been crossed and that new data is not available. The clock transition at point F does cause a burst read of data D128 because the RDY signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available. Additional clock transitions, like at point G, will continue to result in burst reads until the next page boundary is crossed between words D255 and D256. FIXED-LENGTH BURST READS: During a fixed-length burst mode read, four or eight words of data may be burst from the device, depending upon the configuration. The device supports a linear or interleaved burst mode. The burst sequence is shown on page 16. The RDY output remains high (B10 = 0) during fixed-length bursts. The "Four-word Burst Read Waveform" on page 28 illustrates a fixed-length burst cycle. As in the continuous burst read, the data D0 is valid asynchronously from point A, the time when the addresses are latched. D0 is valid within 4 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) 13.5 ns of the clock edge for the specified clock latency (shown for the case of a latency of four). The low-to-high transition of the clock at point C results in D1 being read. Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the read cycle. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins. ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical "1". The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase commands. CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during Chip Erase except Erase Suspend will be ignored. PLANE ERASE: As a alternative to a full chip erase, the device is organized into two planes (32M) or four planes (64M) that can be individually erased. The plane erase command is a sixbus cycle operation. The plane whose address is valid at the sixth falling edge of WE will be erased provided none of the sectors within the plane are protected. SECTOR ERASE: As an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose address is valid at the sixth falling edge of WE will be erased provided the given sector has not been protected. WORD PROGRAMMING: The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The programming address and data are latched in the fourth cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. FLEXIBLE SECTOR PROTECTION: The AT49SN6416(T)/3208(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a twobus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a six-bus cycle Softlock command must be issued to the selected sector. 5 1605C-FLASH-03/02 HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection mode can be enabled by issuing a six-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. * When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. * When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP Hard lock 0 0 Soft lock 0 1 Erase/ Prog Allowed? Yes No VPP VCC/5V VCC/5V WP 0 0 Comments No sector is locked Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is enabled. The sector cannot be unlocked. No sector is locked. Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is overridden and the sector is not locked. Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. Erase and Program Operations cannot be performed. VCC/5V 0 1 1 No VCC/5V VCC/5V 1 1 0 0 0 1 Yes No VCC/5V 1 1 0 Yes VCC/5V 1 1 1 No VIL x x x No SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked. Table 2. Sector Protection Status I/O1 0 0 1 1 I/O0 0 1 0 1 Sector Protection Status Sector Not Locked Softlock Enabled Hardlock Enabled Both Hardlock and Softlock Enabled 6 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. The Table 3 on page 12 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49SN6416(T)/3208(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, "00" or "01". If the configuration register is set to "00", the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a "01", a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a "00" or to a "01", any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is "00". Using the four-bus cycle set configuration register command as shown in the Command Definition table on page 13, the value of the configuration register can be changed. Voltages applied to the reset pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below. DATA POLLING: The AT49SN6416(T)/3208(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a "00", during a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see Table 3 on page 12 for more details. If the status bit configuration register is set to a "01", the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 2 and 3. TOGGLE BIT: In addition to Data Polling, the AT49SN6416(T)/3208(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see Table 3 on page 12 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 4 and 5 on page 11. ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5 that indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a byte/word program operation has been successfully performed. The device may also output a "1" on I/O5 if the system tries to program a "1" to a location that was previously programmed to a "0". Only an erase operation can change a "0" back to a "1". If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress. Please see Table 3 on page 12 for more details. 7 1605C-FLASH-03/02 VPP STATUS BIT: The AT49SN6416(T)/3208(T) provides a status bit on I/O3 that provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a "1". Once the VPP status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will output a "0". Please see Table 3 on page 12 for more details. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual plane architecture, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. 128-BIT PROTECTION REGISTER: The AT49SN6416(T)/3208(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition in Hex table on page 13. To lock out block B, the four-bus cycle lock protection register command must be used as shown in the Command Definition in Hex table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the Protection Register Addressing Table on page 14 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. 8 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 5 on page 34. To exit the CFI Query mode, the product ID exit command must be given. If the CFI Query command is given while the part is in the product ID mode, then the product ID exit command must first be given to return the part to the product ID mode. Once in the product ID mode, it will be necessary to give another product ID exit command to return the part to the read mode. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49SN6416(T)/3208(T) in the following ways: (a) VCC sense: if VCC is below 1.4V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP. INPUT LEVELS: While operating with a 1.8V to 1.95V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 2.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V. OUTPUT LEVELS: For the AT49SN6416(T)/3208(T), output high levels are equal to VCCQ 0.1V (not VCC). VCCQ must be regulated between 1.8V - 2.25V. Figure 1. Output Configuration CLK 1 CLK Data Hold (B9 = 0) 2 CLK Data Hold (B9 = 1) I/00 - I/015 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT I/00 - I/015 9 1605C-FLASH-03/02 Figure 2. Data Polling Algorithm (Configuration Register = 00) Figure 3. Data Polling Algorithm (Configuration Register = 01) START START Read I/O7 - I/O0 Addr = VA Read I/O7 - I/O0 Addr = VA YES I/O7 = Data? NO NO NO I/O7 = 1? YES NO I/O3, I/O5 = 1? I/O3, I/O5 = 1? YES Read I/O7 - I/O0 Addr = VA YES Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Write Product ID Exit Command I/O7 = Data? YES NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode Note: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5. 10 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Figure 4. Toggle Bit Algorithm (Configuration Register = 00) Figure 5. Toggle Bit Algorithm (Configuration Register = 01) START START Read I/O7 - I/O0 Read I/O7 - I/O0 Read I/O7 - I/O0 Read I/O7 - I/O0 Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1? NO Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1? NO YES Read I/O7 - I/O0 Twice YES Read I/O7 - I/O0 Twice Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command NO Toggle Bit = Toggle? YES NO Program/Erase Operation Successful, Device in Read Mode Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Write Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1". Note: 1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1". 11 1605C-FLASH-03/02 Table 3. Status Bit Table(1) I/O7 Configuration Register: Read Address In While 00/01 Plane A 00/01 Plane B 00/01 Plane C 00/01 Plane D 00/01 Plane A 00/01 Plane B I/O6 00/01 Plane C 00/01 Plane D 00/01 Plane A 00/01 Plane B I/O2 00/01 Plane C 00/01 Plane D Programming in Plane A Programming in Plane B Programming in Plane C Programming in Plane D Erasing in Plane A Erasing in Plane B Erasing in Plane C Erasing in Plane D Erase Suspended & Read Erasing Sector Erase Suspended & Read Nonerasing Sector Erase Suspended & Program Nonerasing Sector in Plane A Erase Suspended & Program Nonerasing Sector in Plane B Erase Suspended & Program Nonerasing Sector in Plane C Erase Suspended & Program Nonerasing Sector in Plane D I/O7/0 DATA DATA DATA 0/0 DATA DATA DATA DATA I/O7/0 DATA DATA DATA 0/0 DATA DATA DATA DATA I/O7/0 DATA DATA DATA 0/0 DATA DATA DATA DATA I/O7/0 DATA DATA DATA 0/0 TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE 1 DATA DATA DATA TOGGLE DATA DATA DATA DATA 1 DATA DATA DATA TOGGLE DATA DATA DATA DATA 1 DATA DATA DATA TOGGLE DATA DATA DATA DATA 1 DATA DATA DATA TOGGLE 1 1 1 1 1 1 1 1 TOGGLE TOGGLE TOGGLE TOGGLE DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE Note: 1. For the AT49SN3208(T) only plane A and plane B apply in the table above. 12 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Command Definition in (Hex)(1) Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Enter Single-pulse Program Mode Single-pulse Word Program Mode Sector Softlock Sector Unlock Sector Hardlock Erase/Program Suspend Erase/Program Resume Product ID Entry Product ID Exit (3) Bus Cycles 1 6 6 6 4 6 1 6 2 6 1 1 3 3 1 4 4 4 4 4 4 1 1st Bus Cycle Addr Addr 555 555 555 555 555 Addr 555 555 555 xxx PA(6) 555 555 xxx 555 555 555 555 555 555 X55 Data DOUT AA AA AA AA AA DIN AA AA AA B0 30 AA AA FX AA AA AA AA AA AA 98 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data Addr 4th Bus Cycle Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data AAA(2) AAA AAA AAA AAA 55 55 55 55 55 555 555 555 555 555 80 80 80 A0 80 555 555 555 Addr 555 AA AA AA DIN AA AAA AAA AAA 55 55 55 555 PA(6) SA(4) 10 20 30 AAA 55 555 A0 AAA SA (4) 55 70 55 555 80 555 AA AAA 55 SA(4) 40 AAA 555 80 555 AA AAA 55 SA(4)(5) 60 AAA AAA 55 55 xxx(7) 555 90 F0 Product ID Exit(3) Program Burst Configuration Register Read Burst Configuration Register Program Protection Register - Block B Lock Protection Register - Block B Status of Block B Protection Set Configuration Register CFI Query AAA AAA AAA AAA AAA AAA 55 55 55 55 55 55 555 xxx(7) 555 555 555 555 D0 90 C0 C0 90 E0 xxx 005 Addr 080 80 xxx (8) DOUT DIN X0 DOUT(9) 00/01(10) Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don't Care). 2. 3. 4. 5. 6. Since A11 is a Don't Care, AAA can be replaced with 2AA. Either one of the Product ID Exit commands can be used. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 - 22 for details). Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled. PA is the plane address (A21 - A20 for the AT49SN6416(T), A20 - A19 for the AT49SN3208(T)). 7. For the AT49SN3208: For the AT49SN3208T: xxx = 0XX555 Status Read from Plane A xxx = 1XX555 Status Read from Plane A xxx = 1XX555 Status Read from Plane B xxx = 0XX555 Status Read from Plane B For the AT49SN6416: For the AT49SN6416T: xxx = 0XX555 Status Read from Plane A xxx = 3XX555 Status Read from Plane A xxx = 1XX555 Status Read from Plane B xxx = 2XX555 Status Read from Plane B xxx = 2XX555 Status Read from Plane C xxx = 1XX555 Status Read from Plane C xxx = 3XX555 Status Read from Plane D xxx = 0XX555 Status Read from Plane D 8. See "Burst Configuration Register" on page 15. 9. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 10. The default state (after power-up) of the configuration register is "00". 13 1605C-FLASH-03/02 Absolute Maximum Ratings* Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages Except VPP (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V VPP Input Voltage with Respect to Ground ......................................... 0V to 13.0V All Output Voltages with Respect to Ground ...........................-0.6V to V CCQ + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Protection Register Addressing Table Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21 - A8 = 0. 14 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Burst Configuration Register B15 B14 B13 - B11: 0 1(1) 0(1) 1 010 011 100 101 110(1) 0 1(1) 0 1(1) 0 1(1) 0 1(1) 0 1(1) 00(1) 0 1(1) 001 010 111(1) 1. Default State Synchronous Burst Reads Enabled Asynchronous Reads Enabled Four Word Page Eight Word Page Clock Latency of Two Clock Latency of Three Clock Latency of Four Clock Latency of Five Clock Latency of Six RDY Signal is Active Low RDY Signal is Active High Hold Data for One Clock Hold Data for Two Clocks RDY Asserted during Clock Cycle in which Data is Valid RDY Asserted One Clock Cycle before Data is Valid Interleaved Burst Sequence Linear Burst Sequence Burst Starts and Data Output on Falling Clock Edge Burst Starts and Data Output on Rising Clock Edge Reserved for Future Use Wrap Burst Within Burst length set by B2 - B0 Don't Wrap Accesses Within Burst Length set by B2 - B0 Four-word Burst Eight-word Burst Continuous Burst B10 B9 B8 B7 B6 B5 - B4 B3 B2 - B0 Note: Clock Latency versus Input Clock Frequency Minimum Clock Latency (Minimum Number of Clocks Following Address Latch) 6 4 2 Input Clock Frequency 54 MHz 40 MHz 20 MHz 15 1605C-FLASH-03/02 Table 4. Sequence and Burst Length Burst Addressing Sequence (Decimal) 4-word Burst Length B2 - B0 = 001 Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8-word Burst Length B2 - B0 = 010 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... ... ... ... Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 ... Continuous Burst B2 - B0 = 111 Linear 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20 15-16-17-18-19-20-21 ... 1 1 1 1 1 1 1 1 ... ... 1 1 ... ... ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... N/A N/A N/A N/A ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-1213 7-8-9-10-11-12-1314 ... ... N/A N/A N/A N/A N/A N/A N/A N/A ... ... 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20 15-16-17-18-19-20-21 Start Addr. (Decimal) 0 1 2 3 4 5 6 7 ... 14 15 ... 0 1 2 3 4 5 6 7 ... 14 15 Wrap B3 = 0 0 0 0 0 0 0 0 0 ... 0 0 ... Wrap B3 = 1 16 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Memory Organization - AT49SN3208 x16 Plane A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A20 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF Plane B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Memory Organization - AT49SN3208 (Continued) x16 Address Range (A20 - A0) E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 17 1605C-FLASH-03/02 Memory Organization - AT49SN3208T x16 Plane B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A20 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF Memory Organization - AT49SN3208T (Continued) x16 Plane B B B B B B B B B B B B A A A A A A A A A A A A A A A A A A A A A A A Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K Address Range (A20 - A0) 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1F8FFF 1F9000 - 1F9FFF 1FA000 - 1FAFFF 1FB000 - 1FBFFF 1FC000 - 1FCFFF 1FD000 - 1FDFFF 1FE000 - 1FEFFF 1FF000 - 1FFFFF 18 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Memory Organization - AT49SN6416 x16 Plane A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF Plane B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C Sector SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Memory Organization - AT49SN6416 (Continued) x16 Address Range (A21 - A0) 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 19 1605C-FLASH-03/02 Memory Organization - AT49SN6416 (Continued) x16 Plane C C C C C C C C C C C C C C C D D D D D D D D D Sector SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 288000 - 28FFFF 290000 - 297FFF 298000 - 29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF Memory Organization - AT49SN6416 (Continued) x16 Plane D D D D D D D D D D D D D D D D D D D D D D D Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3FFFFF 20 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Memory Organization - AT49SN6416T x16 Plane D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D C C C C C C C C C C C C C Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF Plane C C C C C C C C C C C C C C C C C C C B B B B B B B B B B B B B B B B B B B B B B B B B B B Sector SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Memory Organization - AT49SN6416T (Continued) x16 Address Range (A21 - A0) 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 -29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 21 1605C-FLASH-03/02 Memory Organization - AT49SN6416T (Continued) x16 Plane B B B B B A A A A A A A A A A A A A A A A Sector SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF Memory Organization - AT49SN6416T (Continued) x16 Plane A A A A A A A A A A A A A A A A A A A A A A A Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K Address Range (A21 - A0) 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3F8FFF 3F9000 - 3F9FFF 3FA000 - 3FAFFF 3FB000 - 3FBFFF 3FC000 - 3FCFFF 3FD000 - 3FDFFF 3FE000 - 3FEFFF 3FF000 - 3FFFFF 22 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) DC and AC Operating Range AT49SN6416(T)/3208(T) - 90 Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 1.65V - 1.95V Operating Modes Mode Read Burst Read Program/Erase(3) Standby/Program Inhibit CE VIL VIL VIL VIH X Program Inhibit X X Output Disable Reset Product Identification A1 - A21 = VIL, A9 = VH(3), A0 = VIL A1 - A21 = VIL, A9 = VH(3), A0 = VIH Software Notes: (5) OE VIL VIL VIH X(1) X VIL X VIH X WE VIH VIH VIL X VIH X X X X RESET VIH VIH VIH VIH VIH VIH X VIH VIL VPP(6) X X VIHPP(7) X X X VILPP(8) X X Ai Ai Ai Ai X I/O DOUT DOUT DIN High Z X X High Z X High Z Hardware VIL VIL VIH VIH Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) VIH A0 = V IL, A1 - A21 = V IL A0 = VIH, A1 - A21 = VIL 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 001FH; Device Code: 00DB - AT49SN3208; 00D1 - AT49SN3208T; 00DC - AT49SN6416; 00D8H - AT49SN6416T. 5. See details under "Software Product Identification Entry/Exit" on page 32. 6. The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 12.0V 0.5V. 7. VIHPP (min) = 1.2V. 8. VILPP (max) = 0.8V. 23 1605C-FLASH-03/02 DC Characteristics Symbol ILI ILO ISB1 ICC (1) Parameter Input Load Current Output Leakage Current V CC Standby Current CMOS V CC Active Current V CC Read While Erase Current V CC Read While Write Current Input Low Voltage Input High Voltage Output Low Voltage Condition VIN = 0V to VCC VI/O = 0V to VCC CE = V CCQ - 0.3V to VCC f = 54 MHz; IOUT = 0 mA f = 54 MHz; IOUT = 0 mA f = 54 MHz; IOUT = 0 mA Min Max 1 1 10 30 50 50 0.4 Units A A A mA mA mA V V ICCRE ICCRW VIL VIH VOL V CCQ - 0.4 IOL = 100 A IOL = 2.1 mA IOH = -100 A IOH = -400 A V CCQ - 0.1 1.4 0.1 0.25 V VOH Output High Voltage V Note: 1. In the erase mode, ICC is 30 mA. Input Test Waveforms and Measurement Level 1.4V AC DRIVING LEVELS 0.4V 0.9V AC MEASUREMENT LEVEL tR, tF < 5 ns Output Test Load VCCQ 1.8K OUTPUT PIN 1.3K 30 pF Pin Capacitance f = 1 MHz, T = 25C(1) Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is characterized and is not 100% tested. 24 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) AC Asynchronous Read Timing Characteristics Symbol tACC1 tACC2 tCE tOE tAHAV tAVLP tAVHP tAAV tDF tRO Parameter Access, AVD To Data Valid Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid Address Hold from AVD AVD Low Pulse Width AVD High Pulse Width Address Valid to AVD CE, OE High to Data Float RESET to Output Delay 9 10 10 10 25 150 Min Max 90 90 90 45 Units ns ns ns ns ns ns ns ns ns ns AVD Pulsed Asynchronous Read Cycle Waveform(1)(2) tCE CE tDF I/O0-I/O15 tACC2 A0 -A21 tAAV tAVHP tAVLP tACC1 OE tRO RESET tOE tAHAV DATA VALID tDF AVD (1) Notes: 1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable. 2. CLK may be static high or static low. Asynchronous Read Cycle Waveform(1)(2)(3)(4) tRC A0 - A21 ADDRESS VALID CE tCE OE tOE tDF tACC2 tOH RESET HIGH Z tRO OUTPUT VALID I/O0 - I/O15 Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. AVD and CLK should be tied low. 25 1605C-FLASH-03/02 AC Asynchronous Read Timing Characteristics Symbol tACC1 tACC2 tCE tOE tAHAV tAVLP tAVHP tAAV tDF tRO tPAA Parameter Access, AVD To Data Valid Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid Address Hold from AVD AVD Low Pulse Width AVD High Pulse Width Address Valid to AVD CE, OE High to Data Float RESET to Output Delay Page Address Access Time 9 10 10 10 25 150 20 Min Max 90 90 90 45 Units ns ns ns ns ns ns ns ns ns ns ns Page Read Cycle Waveform 1(1)(2) tCE CE tDF I/O0-I/O15 tACC2 (2) DATA VALID tDF A2 -A21 tAAV tAHAV tACC2 A0 -A1 (2) tPAA AVD (1) tAAV tAVHP tAVLP tAHAV tACC1 OE tRO RESET tOE Notes: 1. After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable. 2. The diagram shown is for a four-word page read. For an eight-word page read A0 - A1 becomes A0 - A2 and A2 - A21 becomes A3 - A21. Page Read Cycle Waveform 2(1)(2) tCE CE tDF I/O0-I/O15 tACC2 (2) DATA VALID tDF A2 -A21 tPAA tACC2 A0 -A1 (2) AVD (1) VIL tOE tRO RESET OE Notes: 1. AVD may remain low as long as the page address is stable. 2. The diagram shown is for a four-word page read. For an eight-word page read A0 - A1 becomes A0 - A2 and A2 - A21 becomes A3 - A21. 26 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) AC Burst Read Timing Characteristics Symbol tCLK tCKH tCKL tCKRT tCKFT tACK tAVCK tCECK tCKAV tQHCK tAHCK tCKRY tCEAV tAAV tAHAV tCKQV tCEQZ Parameter CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Address Valid to Clock AVD Low to Clock CE Low to Clock Clock to AVD High Output Hold from Clock Address Hold from Clock Clock to RDY Delay CE Setup to AVD Address Valid to AVD Address Hold From AVD CLK to Data Delay CE High to Output High-Z 10 10 9 13.5 10 7 7 7 3 5 10 13.5 Min 18.5 4 4 5 5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Burst Read Cycle Waveform tCLK CLK tAHCK tCECK CE tCE tCEAV tAVCK AVD (2) tCKH ... ... tCKL ... tACK tCKAV tAAV tAHAV tQHCK D0 D1 ... D126 tCKQV tCEQZ I/O0-I/O15 D127 D128 D129 A0-A21 OE tCKRY RDY (1) tCKRY Notes: 1. The RDY signal (solid line) shown is for a burst configuration register setting of B10 and B8 = 0. The RDY Signal (dashed line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. After the high-to-low transition on AVD, AVD may remain low. 27 1605C-FLASH-03/02 Burst Read Waveform (Clock Latency of 4) A CLK B C ... D E F G CE AVD OE A0-A21 VALID I/O0-I/O15 D0 D1 ... D126 D127 D128 D129 RDY (1) Note: 1. Solid line reflects a B10 and B8 setting of 0 in the configuration register. Dashed line reflects a B10 setting of 0 and B8 setting of 1 in the configuration register. Four-word Burst Read Waveform (Clock Latency of 4) A CLK B C CE AVD OE A0-A21 VALID I/O0-I/O15 D0 D1 D2 D3 28 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) AC Word Load Characteristics 1 Symbol tAS tAHAV tAVLP tDS tDH tCEAV tWP tWPH tWEAV tCEAV Parameter Address, CE Setup Time to AVD High Address Hold Time from AVD High AVD Low Pulse Width Data Setup Time Data Hold Time CE Setup to AVD CE or WE Low Pulse Width CE or WE High Pulse Width WE High Time to AVD Low CE High Time to AVD Low Min 10 9 10 15 0 10 70 25 25 25 Max Units ns ns ns ns ns ns ns ns ns ns AC Word Load Waveforms 1 WE Controlled(1) CE I/O0-I/O15 DATA VALID A0 -A21 tAS AVD tAVLP tAHAV tDS tDH tWEAV tWP WE Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. CE Controlled(1) WE I/O0-I/O15 DATA VALID A0 -A21 tAS AVD tAVLP tCEAV CE tWP tAHAV tDS tDH tCEAV Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. 29 1605C-FLASH-03/02 AC Word Load Characteristics 2 Symbol tAS tAH tDS tDH tWP tWPH Parameter Address Setup Time to WE and CE Low Address Hold Time Data Setup Time Data Hold Time CE or WE Low Pulse Width CE or WE High Pulse Width Min 0 20 20 0 35 25 Max Units ns ns ns ns ns ns AC Word Load Waveforms 2 WE Controlled(1) CE I/O0-I/O15 DATA VALID A0 -A21 tDS tDH tAH tAS WE tWP AVD VIL Note: 1. The CLK input should not toggle. CE Controlled(1) WE I/O0-I/O15 DATA VALID A0 -A21 tDS tAS CE AVD VIL tAH tWP tDH Note: 1. The CLK input should not toggle. 30 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Program Cycle Characteristics Symbol tBP tBPVPP tSEC1 tSEC2 tES tPS Parameter Word Programming Time (V pp = VCC) Word Programming Time (V PP > 11.5V) Sector Erase Cycle Time (4K word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Min Typ 22 10 100 500 15 10 Max Units s s ms ms s s Program Cycle Waveforms OE(1) CE I/O0 -I/O15 XXAA XX55 XXA0 INPUT DATA A0 -A21 555 AAA 555 ADDR AVD WE Sector, Plane or Chip Erase Cycle Waveforms OE(1) CE I/O0 -I/O15 XXAA XX55 XX80 XXAA XX55 Note3 A0 -A21 555 AAA 555 555 AAA Note2 AVD WE Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For plane or sector erase, the address depends on what plane or sector is to be erased. (See note 3 and 5 under Command Definitions on page 13.) 3. For chip erase, the data should be XX10H, for plane erase, the data should be XX20H, and for sector erase, the data should be XX30H 4. The waveforms shown above use the WE controlled AC Word Load Waveforms 1. 31 1605C-FLASH-03/02 Data Polling Characteristics Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 10 10 Typ Max Units ns ns ns Write Recovery Time 0 ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in page 25. Data Polling Waveforms WE CE OE I/O7 A0-A21 Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time (2) Min 10 10 Typ Max Units ns ns ns 50 0 ns ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in page 25. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 32 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 555 Software Product Identification Exit(1)(6) LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS LOAD DATA 55 TO ADDRESS AAA LOAD DATA 55 TO ADDRESS AAA EXIT PRODUCT IDENTIFICATION MODE(4) LOAD DATA F0 TO ADDRESS 555 LOAD DATA 90 TO ADDRESS xxx(7) EXIT PRODUCT IDENTIFICATION MODE(4) ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) Notes: 1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex); A12 - A21 (Don't Care). 2. A1 - A21 = V IL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH Device Code: 00DB - AT49SN3208; 00D1 - AT49SN3208T; 00DC - AT49SN6416; 00D8H - AT49SN6416T. 6. Either one of the Product ID Exit commands can be used. 7. For the AT49SN3208: For the AT49SN3208T: xxx = 0XX555 Status Read from Plane A xxx = 1XX555 Status Read from Plane B For the AT49SN6416: xxx = 0XX555 Status Read from Plane A xxx = 1XX555 Status Read from Plane B xxx = 2XX555 Status Read from Plane C xxx = 3XX555 Status Read from Plane D xxx = 1XX555 Status Read from Plane A xxx = 0XX555 Status Read from Plane B For the AT49SN6416T: xxx = 3XX555 Status Read from Plane A xxx = 2XX555 Status Read from Plane B xxx = 1XX555 Status Read from Plane C xxx = 0XX555 Status Read from Plane D If a read status has been entered for a plane, any read from this plane will be a status read while any read of another plane will be a memory read, either random or burst. Program or erase operations cannot be performed while one of the planes is in the read status mode. 33 1605C-FLASH-03/02 Table 5. Common Flash Interface Definition for AT49SN6416(T)/3208(T) Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h AT49SN3208(T) 0051h 0052h 0059h 0002h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 00B5h 00C5h 0004h 0000h 0009h 000Fh 0004h 0000h 0003h 0003h 0016h 0001h 0000h 0000h 0000h 0002h 003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h AT49SN6416(T) 0051h 0052h 0059h 0002h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 00B5h 00C5h 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h Typ block erase - 500 ms Typ chip erase, 32M bytes - 32,300 ms, 64M bytes - 64,300 ms Max word write/typ time n/a Max block erase/typ block erase Max chip erase/ typ chip erase Device size x16 device x16 device Multiple byte write not supported Multiple byte write not supported 2 regions, x = 2 64K bytes, 32M - Y = 62, 64M - Y = 126 64K bytes, 32M - Y = 62, 64M - Y = 126 64K bytes, Z = 256 64K bytes, Z = 256 8K bytes, Y = 7 8K bytes, Y = 7 8K bytes, Z = 32 8K bytes, Z = 32 VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write - 16 s Comments "Q" "R" "Y" 34 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Table 5. Common Flash Interface Definition for AT49SN6416(T)/3208(T) (Continued) Address AT49SN3208(T) AT49SN6416(T) Comments VENDOR SPECIFIC EXTENDED QUERY 41h 42h 43h 44h 45h 46h 0050h 0052h 0049h 0031h 0030h 00BFh 0050h 0052h 0049h 0031h 0030h 00BFh "P" "R" "I" Major version number, ASCII Minor version number, ASCII Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 - chip erase supported, 0 - no, 1 - yes - erase suspend supported, 0 - no, 1 - yes - program suspend supported, 0 - no, 1 - yes - simultaneous operations supported, 0 - no, 1 - yes - burst mode read supported, 0 - no, 1 - yes - page mode read supported, 0 - no, 1 - yes - queued erase supported, 0 - no, 1 - yes - protection bits supported, 0 - no, 1 - yes 47h 0000h AT49SN3208T or 0001h AT49SN3208 0007h 0000h AT49SN6416T or 0001h AT49SN6416 0007h Bit 8 - top ("0") or bottom ("1") boot block device undefined bits are "0" 48h Bit 0 - 4 word linear burst with wrap around, 0 - no, 1 - yes Bit 1 - 8 word linear burst with wrap around, 0 - no, 1 - yes Bit 2 - continuos burst undefined bits are "0" Bit 0 - 4 word page, 0 - no, 1 - yes Bit 1 - 8 word page, 0 - no, 1 - yes Undefined bits are "0" Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register - 2*n # of bytes in the user prog section of prot register - 2*n 49h 0003h 0003h 4Ah 4Bh 4Ch 0080h 0003h 0003h 0080h 0003h 0003h 35 1605C-FLASH-03/02 AT49SN6416(T) Ordering Information tACC (ns) 90 90 ICC (mA) Active 25 25 Standby 0.01 0.01 Ordering Code AT49SN6416-90CI AT49SN6416T-90CI Package 55C1 55C1 Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Package Type 55C1 55-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 36 AT49SN6416(T)/3208(T) 1605C-FLASH-03/02 AT49SN6416(T)/3208(T) Packaging Information - AT49SN6416(T) 55C1 - CBGA D 0.12 C C Seating Plane E Side View Top View A A1 1.375 mm Ref 87 6 D1 5 4 3 21 A B C D E F G COMMON DIMENSIONS (Unit of Measure = mm) E1 SYMBOL A A1 D D1 MIN - 0.23 7.90 NOM - - 8.00 5.25 TYP 10.90 11.00 4.50 TYP 0.75 TYP 0.35 TYP 11.10 MAX 1.00 - 8.10 NOTE e 3.25 mm Ref e Ob E E1 e Bottom View Ob 3/20/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 55C1, 55-ball (8 x 7 Array), 8 x 11 x 1.0 mm Body, 0.75 mm Ball Pitch Ceramic Ball Grid Array Package (CBGA) DRAWING NO. 55C1 REV. A R 37 1605C-FLASH-03/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1605C-FLASH-03/02 xM |
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